This invention relates to a method of manufacturing a semiconductor device comprising a trench gate field effect device. The device may be, for example, an insulated gate field effect power transistor or an insulated gate bipolar transistor. The invention also relates to a semiconductor device manufactured by such a method.
U.S. Pat. No. 5,378,655 (our reference: PHB33836) describes a method of manufacturing a semiconductor device comprising a trench gate field effect device wherein a semiconductor body having first and second major surfaces is provided having a first region of one conductivity type and a second region of the opposite conductivity type separating the first region from the first major surface. A trench is etched through the second semiconductor region and then a gate is provided within the trench with, in the example described in U.S. Pat. No. 5,378,655, the gate being an insulated gate having a gate dielectric region separating a conductive gate region from the trench walls. A source region of the one conductivity type separated from the first region by the second region is formed adjacent the trench so that a conduction channel area of the second region adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate. Typically, the trench will define a regular array of parallel source cells each bounded by the trench.
As shown in the drawings of U.S. Pat. No. 5,378,655, the trench extends beyond the second region into the first region. Where such a device is operated in a reverse bias or blocking mode, large electrical fields can build up at the relatively sharp corners of the trench leading to breakdown at these points. It has previously been proposed, as shown in, for example, U.S. Pat. No. 5,387,528 (our reference: PHB33804), to provide each source cell with a central relatively highly doped deep region of the opposite conductivity type so as to move the avalanche breakdown point away from the trench corners into the centre of the source cell so as to enable the onset of avalanche breakdown to be delayed until higher voltages and to enable breakdown, if it does occur, to happen in a more controlled and reproducible manner. However, the introduction of such relatively highly doped central regions places a constraint on the minimum dimensions of the source cells which in turn places a constraint on the minimum on-resistance of the device because, for a given semiconductor surface area, the on-resistance is related to the channel width which itself is related to the size of the source cells.